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Travelled to:
3 × Germany
7 × USA
Collaborated with:
G.d.Veciana C.He J.T.Russell S.Pillai A.Ramachandran S.W.Director M.Lajolo V.S.Lapinskii J.Guo S.Bijansky H.P.Peixoto A.Royo J.C.López A.V.Zykov E.Mizan A.Subramanian
Talks about:
design (5) perform (4) embed (4) cluster (3) system (3) vliw (3) nanotechnolog (2) probabilist (2) architectur (2) framework (2)

Person: Margarida F. Jacome

DBLP DBLP: Jacome:Margarida_F=

Contributed to:

DATE 20062006
DAC 20052005
DAC 20042004
DAC 20032003
DATE 20032003
ICSE 20032003
PDP 20032003
DAC 20012001
DATE 19991999
DAC 19981998
DAC 19921992

Wrote 13 papers:

DATE-2006-HeJ #configuration management #framework #named #synthesis
RAS-NANO: a reliability-aware synthesis framework for reconfigurable nanofabrics (CH, MFJ), pp. 1179–1184.
DAC-2005-ZykovMJVS #architecture #novel #performance #trade-off
High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offs (AVZ, EM, MFJ, GdV, AS), pp. 270–273.
DAC-2004-JacomeHVB #design #fault #paradigm #probability
Defect tolerant probabilistic design paradigm for nanotechnologies (MFJ, CH, GdV, SB), pp. 596–601.
DAC-2003-RamachandranJ #embedded #energy #memory management #named #performance
Xtream-Fit: an energy-delay efficient data memory subsystem for embedded media processing (AR, MFJ), pp. 137–142.
DAC-2003-RussellJ #architecture #component #embedded #evaluation #performance
Architecture-level performance evaluation of component-based embedded systems (JTR, MFJ), pp. 396–401.
DATE-2003-PillaiJ #clustering #scheduling
Compiler-Directed ILP Extraction for Clustered VLIW/EPIC Machines: Predication, Speculation and Modulo Scheduling (SP, MFJ), pp. 10422–10427.
ICSE-2003-RussellJ #architecture #embedded #evaluation #performance
Embedded Architect: A Tool for Early Performance Evaluation of Embedded Software (JTR, MFJ), pp. 824–825.
PDP-2003-HeLJ #approach #case study #queue
A Case Study of a System Level Approach to Exploration of Queuing Management Schemes for Input Queue Packet Switches (CH, ML, MFJ), pp. 401–408.
DAC-2001-JacomeVP #architecture #clustering
Clustered VLIW Architectures with Predicated Switching (MFJ, GdV, SP), pp. 696–701.
DAC-2001-LapinskiiJV #clustering
High-Quality Operation Binding for Clustered VLIW Datapaths (VSL, MFJ, GdV), pp. 702–707.
DATE-1999-JacomePRL #design
The Design Space Layer: Supporting Early Design Space Exploration for Core-Based Designs (MFJ, HPP, AR, JCL), pp. 676–683.
DAC-1998-VecianaJG #algorithm #constraints #performance #probability
Hierarchical Algorithms for Assessing Probabilistic Constraints on System Performance (GdV, MFJ, JHG), pp. 251–256.
DAC-1992-JacomeD #design #framework #process
Design Process Management for CAD Frameworks (MFJ, SWD), pp. 500–505.

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