BibSLEIGH — Soonhoi

Travelled to:

3 × France
4 × Germany
9 × USA

Collaborated with:

S.Kim H.Oh D.Kim H.Yang R.Gupta Y.Yi S.Park H.Park C.Im M.Kim M.Oh W.Sung J.Kim J.Choi S.Kang I.Bacivarov L.Thiele Y.Joo C.Park D.Yun Y.Kee J.Kim W.Jeun Y.Ko T.Kim M.Kim H.Ha K.Oh M.Sim R.Leupers A.Vajda M.Bekooij R.Dömer A.Nohl

Talks about:

simul (6) system (5) time (5) techniqu (4) embed (4) use (4) architectur (3) multimedia (3) processor (3) synchron (3)

Person: Soonhoi Ha

DBLP: Ha:Soonhoi

Contributed to:

2014

2013

2012

2011

2009

2008

2007

2006

2005

2004

2002

2001

1998

Wrote 22 papers:

DAC-2014-KangYKBHT #fault tolerance: Static Mapping of Mixed-Critical Applications for Fault-Tolerant MPSoCs (SHK, HY, SK, IB, SH, LT), p. 6.
DAC-2014-KoKYKH #cpu #gpu #platform #simulation: Hardware-in-the-loop Simulation for CPU/GPU Heterogeneous Platforms (YK, TK, YY, MK, SH), p. 6.
DATE-2014-KangYKBHT #manycore #optimisation: Reliability-aware mapping optimization of multi-core systems with mixed-criticality (SHK, HY, SK, IB, SH, LT), pp. 1–4.
DAC-2013-KimOCHH #distributed #embedded #estimation #novel: A novel analytical method for worst case response time estimation of distributed embedded systems (JK, HO, JC, HH, SH), p. 10.
DAC-2012-ChoiOKH #architecture #data flow #graph #manycore: Executing synchronous dataflow graphs on a SPM-based multicore architecture (JC, HO, SK, SH), pp. 664–671.
DAC-2011-YunKKH #embedded #manycore #parallel #simulation: Simulation environment configuration for parallel simulation of multicore embedded systems (DY, JK, SK, SH), pp. 345–350.
DATE-2009-JooKH #architecture #communication: On-chip communication architecture exploration for processor-pool-based MPSoC (YPJ, SK, SH), pp. 466–471.
DATE-2009-LeupersVBHDN #exclamation #programming: Programming MPSoC platforms: Road works ahead! (RL, AV, MB, SH, RD, AN), pp. 1584–1589.
DATE-2009-YangH #parallel #pipes and filters #scheduling: Pipelined data parallel task mapping/scheduling technique for MPSoC (HY, SH), pp. 69–74.
DATE-2008-KimPH #architecture #multi: Architecture Exploration of NAND Flash-based Multimedia Card (SK, CP, SH), pp. 218–223.
DATE-2007-KimHG #multi #named #simulation #transaction: CATS: cycle accurate transaction-driven simulation with multiple processor simulators (DK, SH, RG), pp. 749–754.
DATE-2007-ParkPH #memory management #novel #stack: A novel technique to use scratch-pad memory for stack management (SP, HwP, SH), pp. 1478–1483.
DATE-2006-KimHG #execution #parallel #using: Parallel co-simulation using virtual synchronization with redundant host execution (DK, SH, RG), pp. 1151–1156.
DATE-2006-ParkOPSH #embedded #source code: Dynamic code overlay of SDF-modeled programs on low-end embedded systems (HwP, KO, SP, MmS, SH), pp. 945–946.
DAC-2005-KimYH #using: Trace-driven HW/SW cosimulation using virtual synchronization technique (DK, YY, SH), pp. 345–348.
LCTES-2004-ImH #multi #realtime #scalability #scheduling #using: Dynamic voltage scaling for real-time multi-task scheduling using buffers (CI, SH), pp. 88–94.
PDP-2004-KeeKJH: Atomic Page Update Methods for OpenMP-Aware Software DSM (YSK, JSK, WCJ, SH), pp. 144–151.
DAC-2002-OhH #data flow #graph #multi #performance #synthesis: Efficient code synthesis from extended dataflow graphs for multimedia applications (HO, SH), pp. 275–280.
LCTES-SCOPES-2002-OhH #data flow #multi #performance #synthesis: Fractional rate dataflow model and efficient code synthesis for multimedia applications (HO, SH), pp. 12–17.
LCTES-OM-2001-KimH #embedded #hybrid #power management #realtime #runtime #scalability: Hybrid Run-time Power Management Technique for Real-time Embedded System with Voltage Scalable Processor (MK, SH), pp. 11–19.
DAC-1998-OhH #data flow #design #graph: Rate Optimal VLSI Design from Data Flow Graph (MO, SH), pp. 118–121.
DATE-1998-SungH #hardware: Optimized Timed Hardware Software Cosimulation without Roll-back (WS, SH), pp. 945–946.