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Travelled to:
1 × Germany
1 × India
1 × Mexico
1 × United Kingdom
13 × USA
Collaborated with:
R.Eigenmann G.Voskuilen M.D.Powell F.Ahmad K.Roy S.A.R.Jafri T.A.Johnson B.Falsafi M.Thottethodi E.Schuchman S.Yang C.Cher A.L.Hosking M.A.Gomaa A.Agarwal S.T.Chakradhar A.Raghunathan J.Hasan A.Jalote C.E.Brodley S.Gopal J.E.Smith G.S.Sohi A.M.Amin S.Wereley S.C.Jacobson H.Li S.Bhunia Y.Chen S.W.Kim C.Ooi
Talks about:
optim (5) specul (4) power (4) cach (4) architectur (3) perform (3) reduc (3) high (3) decomposit (2) submicron (2)

Person: T. N. Vijaykumar

DBLP DBLP: Vijaykumar:T=_N=

Contributed to:

ASPLOS 20142014
ASPLOS 20132013
ASPLOS 20122012
ASPLOS 20102010
HPCA 20102010
PLDI 20082008
PPoPP 20072007
ASPLOS 20062006
HPCA 20052005
ASPLOS 20042004
PLDI 20042004
DATE 20032003
HPCA 20032003
HPCA 20022002
HPCA 20012001
PPoPP 20012001
HPCA 19981998

Wrote 18 papers:

High-performance fractal coherence (GV, TNV), pp. 701–714.
ASPLOS-2013-JafriVV #dependence #named #performance
Wait-n-GoTM: improving HTM performance by serializing cyclic dependencies (SARJ, GV, TNV), pp. 521–534.
ASPLOS-2012-AhmadCRV #clustering #named #optimisation #pipes and filters
Tarazu: optimizing MapReduce on heterogeneous clusters (FA, STC, AR, TNV), pp. 61–74.
ASPLOS-2010-AhmadV #maintenance #optimisation
Joint optimization of idle and cooling power in data centers while maintaining response time (FA, TNV), pp. 243–256.
HPCA-2010-JafriTV #named #transaction
LiteTM: Reducing transactional state overhead (SARJ, MT, TNV), pp. 1–12.
PLDI-2008-AminTVWJ #automation #programmable
Automatic volume management for programmable microfluidics (AMA, MT, TNV, SW, SCJ), pp. 56–67.
PPoPP-2007-JohnsonEV #composition #concurrent #empirical #optimisation #thread
Speculative thread decomposition through empirical optimization (TAJ, RE, TNV), pp. 205–214.
ASPLOS-2006-SchuchmanV #architecture #program transformation #quantum
A program transformation and architecture support for quantum uncomputation (ES, TNV), pp. 252–263.
HPCA-2005-HasanJVB #smt
Heat Stroke: Power-Density-Based Denial of Service in SMT (JH, AJ, TNV, CEB), pp. 166–177.
ASPLOS-2004-CherHV #analysis #garbage collection #hardware
Software prefetching for mark-sweep garbage collection: hardware analysis and software redesign (CYC, ALH, TNV), pp. 199–210.
ASPLOS-2004-GomaaPV #named #operating system #smt
Heat-and-run: leveraging SMT and CMP to manage power density through the operating system (MAG, MDP, TNV), pp. 260–270.
PLDI-2004-JohnsonEV #composition #concurrent #thread
Min-cut program decomposition for thread-level speculation (TAJ, RE, TNV), pp. 59–70.
DATE-2003-AgarwalRV #architecture #pipes and filters
Exploring High Bandwidth Pipelined Cache Architecture for Scaled Technology (AA, KR, TNV), pp. 10778–10783.
HPCA-2003-LiBCVR #reduction
Deterministic Clock Gating for Microprocessor Power Reduction (HL, SB, YC, TNV, KR), pp. 113–122.
HPCA-2002-YangPFV #design #energy
Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay (SHY, MDP, BF, TNV), pp. 151–161.
HPCA-2001-YangPFRV #approach #architecture
An Integrated Circuit/Architecture Approach to Reducing Leakage in Deep-Submicron High-Performance I-Caches (SHY, MDP, BF, KR, TNV), pp. 147–157.
PPoPP-2001-KimOEFV #analysis #execution #framework #optimisation
Reference idempotency analysis: a framework for optimizing speculative execution (SWK, ClO, RE, BF, TNV), pp. 2–11.
HPCA-1998-GopalVSS #version control
Speculative Versioning Cache (SG, TNV, JES, GSS), pp. 195–205.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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