BibSLEIGH — A_Richard

Travelled to:

10 × USA
2 × United Kingdom

Collaborated with:

S.Devadas ∅ A.L.Sangiovanni-Vincentelli D.O.Pederson A.Ghosh R.K.Brayton H.H.Hse A.Tabbara E.Siepmann G.S.Whitcomb B.Lin J.T.Deutsch Z.Wei Y.Cao N.Ghazal J.M.Rabaey F.L.Chan M.D.Spiller J.S.Roychowdhury P.Ashar A.Casotto H.T.Ma S.H.Hwang Y.H.Kim G.K.Jacob G.D.Hachtel K.H.Keller S.Ellis A.A.Malik J.S.Young J.MacDonald M.Shilman P.N.Hilfinger

Talks about:

design (7) circuit (5) level (5) sequenti (4) base (4) verif (3) simul (3) logic (3) delay (3) test (3)

Person: A. Richard Newton

DBLP: Newton:A=_Richard

Facilitated 2 volumes:

Contributed to:

2004

2000

1999

1998

1994

1992

1990

1988

1987

1986

1984

1982

1980

Wrote 24 papers:

ICPR-v1-2004-HseN #recognition #sketching #using: Sketched Symbol Recognition using Zernike Moments (HHH, ARN), pp. 367–370.
ICPR-v4-2004-WeiCN #image: Digital Image Restoration by Exposure-Splitting and Registration (ZW, YC, ARN), pp. 657–660.
DAC-2000-GhazalNR #performance #predict: Predicting performance potential of modern DSPs (NG, ARN, JMR), pp. 332–335.
DAC-1999-TabbaraBN #constraints #trade-off: Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints (AT, RKB, ARN), pp. 725–730.
DAC-1998-ChanSN #design #named: WELD — An Environment for Web-based Electronic Design (FLC, MDS, ARN), pp. 146–151.
DAC-1998-YoungMSTHN #design #embedded #java #refinement #specification #using: Design and Specification of Embedded Systems in Java Using Successive, Formal Refinement (JSY, JM, MS, AT, PNH, ARN), pp. 70–75.
ISSTA-1994-SiepmannN #named #object-oriented #testing: TOBAC: A Test Case Browser for Testing Object-Oriented Software (ES, ARN), pp. 154–168.
DAC-1992-RoychowdhuryNP #linear #simulation: Simulating Lossy Interconnect with High Frequency Nonidealities in Linear Time (JSR, ARN, DOP), pp. 75–80.
DAC-1990-AsharDN #approach #composition: A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines (PA, SD, ARN), pp. 601–606.
DAC-1990-CasottoNS #design: Design Management Based on Design Traces (AC, ARN, ALSV), pp. 136–141.
DAC-1990-GhoshDN #verification: Verification of Interacting Sequential Circuits (AG, SD, ARN), pp. 213–219.
DAC-1990-GhoshDN90a #generative #logic #testing: Sequential Test Generation at the Register-Transfer and Logic Levels (AG, SD, ARN), pp. 580–586.
DAC-1990-MalikBNS #logic #multi: Reduced Offsets for Two-Level Multi-Valued Logic Minimization (AAM, RKB, ARN, ALSV), pp. 290–296.
DAC-1990-WhitcombN #data type #synthesis: Abstract Data Types and High-Level Synthesis (GSW, ARN), pp. 680–685.
DAC-1988-Newton #automation #design: Twenty-Five Years of Electronic Design Automation (ARN), p. 2.
DAC-1987-DevadasMN #abstraction #on the #verification: On the Verification of Sequential Machines at Differing Levels of Abstraction (SD, HKTM, ARN), pp. 271–276.
DAC-1987-LinN #named: KAHLUA: A Hierarchical Circuit Disassembler (BL, ARN), pp. 311–317.
DAC-1986-DevadasN #array #named #synthesis: GENIE: a generalized array optimizer for VLSI synthesis (SD, ARN), pp. 631–637.
DAC-1986-HwangKN #modelling #verification: An accuration delay modeling technique for switch-level timing verification (SHH, YHK, ARN), pp. 227–233.
DAC-1986-JacobNP #analysis #empirical #multi #performance: An empirical analysis of the performance of a multiprocessor-based circuit simulator (GKJ, ARN, DOP), pp. 588–593.
DAC-1984-DeutschN #implementation #multi #simulation: A multiprocessor implementation of relaxation-based electrical circuit simulation (JTD, ARN), pp. 350–357.
DAC-1982-HachtelNS #array #logic #programmable: Techniques for programmable logic array folding (GDH, ARN, ALSV), pp. 147–155.
DAC-1982-KellerNE #design: A symbolic design system for integrated circuits (KHK, ARN, SE), pp. 460–466.
DAC-1980-Newton #challenge #design: The VLSI design challenge of the 80’s (ARN), pp. 343–344.