BibSLEIGH — Pranav

Travelled to:

13 × USA
2 × Germany
2 × United Kingdom

Collaborated with:

A.Gupta M.K.Ganai S.Malik S.Devadas Z.Yang C.Wang S.Cadambi C.Mulpuri F.Fallah V.Tiwari A.R.Newton A.Gupta P.Zhong M.Martonosi J.Monteiro A.Mauskar L.Zhang F.Ivancic I.Shlyakhter A.E.Casavant S.Liu A.Mukaiyama K.Wakabayashi

Talks about:

model (6) base (6) sat (6) simul (4) check (4) techniqu (3) memori (3) comput (3) use (3) decomposit (2)

Person: Pranav Ashar

DBLP: Ashar:Pranav

Contributed to:

2005

2004

2003

2002

2001

1999

1998

1997

1996

1994

1993

1990

Wrote 18 papers:

CAV-2005-IvancicYGGSA #framework #named #platform #verification: F-Soft: Software Verification Platform (FI, ZY, MKG, AG, IS, PA), pp. 301–306.
DAC-2005-GanaiGA #model checking #safety #satisfiability: Beyond safety: customized SAT-based model checking (MKG, AG, PA), pp. 738–743.
DATE-2005-GanaiGA #embedded #memory management #modelling #performance #using #verification: Verification of Embedded Memory Systems using Efficient Memory Modeling (MKG, AG, PA), pp. 1096–1101.
TACAS-2005-GanaiGA #framework #model checking #named #platform #satisfiability #scalability #verification: DiVer: SAT-Based Model Checking Platform for Verifying Large Scale Systems (MKG, AG, PA), pp. 575–580.
CAV-2004-GanaiGA #bound #embedded #model checking #modelling #performance: Efficient Modeling of Embedded Memories in Bounded Model Checking (MKG, AG, PA), pp. 440–452.
CAV-2003-GuptaGWYA #abstraction #satisfiability: Abstraction and BDDs Complement SAT-Based BMC in DiVer (AG, MKG, CW, ZY, PA), pp. 206–209.
DAC-2003-GuptaGWYA #bound #learning #model checking #satisfiability: Learning from BDDs in SAT-based bounded model checking (AG, MKG, CW, ZY, PA), pp. 824–829.
DAC-2002-CadambiMA #functional #hardware #performance #scalability #simulation: A fast, inexpensive and scalable hardware acceleration technique for functional simulation (SC, CM, PA), pp. 570–575.
DAC-2002-GanaiAGZM #algorithm #satisfiability: Combining strengths of circuit-based and CNF-based algorithms for a high-performance SAT solver (MKG, PA, AG, LZ, SM), pp. 747–750.
DAC-2001-GuptaGYA #detection #image #satisfiability: Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation (AG, AG, ZY, PA), pp. 536–541.
DATE-2001-CasavantGLMWA #generative #graph #simulation: Property-specific witness graph generation for guided simulation (AEC, AG, SL, AM, KW, PA), p. 799.
DAC-1999-FallahAD #generative #simulation: Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage (FF, PA, SD), pp. 666–671.
DAC-1998-ZhongAMM #case study #configuration management #problem #satisfiability #using: Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability (PZ, PA, SM, MM), pp. 194–199.
DAC-1997-GuptaMA #formal method #simulation #towards #using #validation: Toward Formalizing a Validation Methodology Using Simulation Coverage (AG, SM, PA), pp. 740–745.
DAC-1996-MonteiroDAM #power management #scheduling: Scheduling Techniques to Enable Power Management (JM, SD, PA, AM), pp. 349–352.
DAC-1994-AsharM #low cost #set: Implicit Computation of Minimum-Cost Feedback-Vertex Sets for Partial Scan and Other Applications (PA, SM), pp. 77–80.
DAC-1993-TiwariAM: Technology Mapping for Lower Power (VT, PA, SM), pp. 74–79.
DAC-1990-AsharDN #approach #composition: A Unified Approach to the Decomposition and Re-Decomposition of Sequential Machines (PA, SD, ARN), pp. 601–606.