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Travelled to:
1 × France
12 × USA
2 × Germany
Collaborated with:
A.Bredenfeld W.Meyer N.V.Shenoy J.Kawa R.H.J.M.Otten P.Groeneveld A.Lock H.Meyr R.A.Bergamaschi M.Payer M.C.McFarland A.C.Parker D.Gope S.Grivet-Talocia V.Jandhyala E.Sentovich J.Douglas A.Khan K.Keutzer J.Fiddler A.L.Sangiovanni-Vincentelli J.Lansford S.Rawat A.Kahng J.Sawicki M.Gianfagna N.Zafar A.Sharan J.M.Rabaey J.Kunkel D.Brophy D.Samani L.Lerner R.Hetherington A.Kuehlmann J.Colgan J.Chilton S.George R.Griffith P.Leventis D.Singh R.Wilson J.Gianelli C.Hamlin K.McElvain S.Leibson I.Bolson R.Tobias
Talks about:
design (7) synthesi (4) platform (3) level (3) programm (2) system (2) model (2) futur (2) autom (2) path (2)

Person: Raul Camposano

DBLP DBLP: Camposano:Raul

Contributed to:

DATE 20122012
DAC 20102010
DAC 20062006
DAC 20052005
DAC 20042004
DAC 20022002
DATE 20022002
DATE 20012001
DAC 19991999
DAC 19961996
DAC 19951995
DAC 19931993
DAC 19911991
DAC 19881988
DAC 19851985

Wrote 17 papers:

Moore meets maxwell (RC, DG, SGT, VJ), pp. 1275–1276.
DAC-2010-KuehlmannCCCGGLS #design #in the cloud #question
Does IC design have a future in the clouds? (AK, RC, JC, JC, SG, RG, PL, DS), pp. 412–414.
DAC-2006-RawatCKSGZS #named #proving #question
DFM: where’s the proof of value? (SR, RC, AK, JS, MG, NZ, AS), pp. 1061–1062.
DAC-2005-WilsonGHMLBTC #framework #platform #question
Structured/platform ASIC apprentices: which platform will survive your board room? (RW, JG, CH, KM, SL, IB, RT, RC), pp. 887–888.
DAC-2004-SentovichCDK #modelling
Business models in IP, software licensing, and services (ES, RC, JD, AK), p. 264.
DAC-2004-ShenoyKC #automation #design #programmable
Design automation for mask programmable fabrics (NVS, JK, RC), pp. 192–197.
DAC-2002-RabaeyKBCSLH #question #what
What’s the next EDA driver? (JMR, JK, DB, RC, DS, LL, RH), p. 652.
DATE-2002-OttenCG #automation #design
Design Automation for Deepsubmicron: Present and Future (RHJMO, RC, PG), pp. 650–657.
DATE-2001-LockCM #framework #platform #programmable #question
The programmable platform: does one size fit all? (AL, RC, HM), pp. 226–227.
DAC-1999-CamposanoKFSL #design #embedded
HW and SW in Embedded System Design: Loveboat, Shipwreck, or Ships Passing in the Night (RC, KK, JF, ALSV, JL), pp. 76–77.
DAC-1996-Camposano #behaviour #synthesis
Behavioral Synthesis (RC), pp. 33–34.
DAC-1995-BredenfeldC #design #graph #integration #tool support #using
Tool Integration and Construction Using Generated Graph-Based Design Representations (AB, RC), pp. 94–99.
DAC-1993-MeyerC #fault #multi #performance #simulation
Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy (WM, RC), pp. 515–519.
DAC-1991-BergamaschiCP #analysis #synthesis #using
Data-Path Synthesis Using Path Analysis (RAB, RC, MP), pp. 591–596.
DAC-1988-Composano #compilation #design #process
Design Process Model in the Yorktown Silicon Compiler (RC), pp. 489–494.
DAC-1988-McFarlandPC #synthesis #tutorial
Tutorial on High-Level Synthesis (MCM, ACP, RC), pp. 330–336.
DAC-1985-Camposano #design #synthesis
Synthesis techniques for digital systems design (RC), pp. 475–481.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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