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Travelled to:
1 × France
1 × Germany
1 × Switzerland
1 × The Netherlands
5 × USA
Collaborated with:
Y.Xie G.Sun D.Niu N.P.Jouppi N.Muralimanohar T.Zhang Y.Bai Z.Li X.Dong Y.Chen Z.Wang D.A.Jiménez M.Poremba S.Gamage P.N.Rao A.Kangarlou R.R.Kompella D.Xu R.Balasubramonian S.Yu A.Jog A.K.Mishra V.Narayanan R.Iyer C.R.Das
Talks about:
memori (4) design (3) cach (3) base (3) awar (3) ram (3) architectur (2) memristor (2) virtual (2) schedul (2)

Person: Cong Xu


Contributed to:

HPCA 20152015
HPCA 20142014
DAC 20132013
DAC 20122012
DATE 20122012
HPDC 20122012
DATE 20112011
DAC 20102010
SAC 20102010

Wrote 10 papers:

HPCA-2015-XuNMBZY0 #architecture #challenge #memory management
Overcoming the challenges of crossbar resistive memory architectures (CX, DN, NM, RB, TZ, SY, YX), pp. 476–488.
HPCA-2014-WangJXSX #adaptation #hybrid #migration #policy
Adaptive placement and migration policy for an STT-RAM-based hybrid cache (ZW, DAJ, CX, GS, YX), pp. 13–24.
HPCA-2014-ZhangPXSX #architecture #memory management #named
CREAM: A Concurrent-Refresh-Aware DRAM Memory architecture (TZ, MP, CX, GS, YX), pp. 368–379.
DAC-2013-XuNMJX #comprehension #design #memory management #multi #trade-off
Understanding the trade-offs in multi-level cell ReRAM memory design (CX, DN, NM, NPJ, YX), p. 6.
DAC-2012-JogMXXNID #architecture #performance
Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs (AJ, AKM, CX, YX, VN, RI, CRD), pp. 243–252.
DATE-2012-SunXX #design #memory management #modelling
Modeling and design exploration of FBDRAM as on-chip memory (GS, CX, YX), pp. 1507–1512.
HPDC-2012-XuGRKKX #cpu #named #scheduling #slicing #virtual machine
vSlicer: latency-aware virtual machine scheduling via differentiated-frequency CPU slicing (CX, SG, PNR, AK, RRK, DX), pp. 3–14.
DATE-2011-XuDJX #design
Design implications of memristor-based RRAM cross-point structures (CX, XD, NPJ, YX), pp. 734–739.
DAC-2010-NiuCXX #process
Impact of process variations on emerging memristor (DN, YC, CX, YX), pp. 877–882.
SAC-2010-BaiXL #virtual machine
Task-aware based co-scheduling for virtual machine system (YB, CX, ZL), pp. 181–188.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.