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Travelled to:
2 × France
2 × Germany
8 × USA
Collaborated with:
L.Leung M.Pedram A.M.Despain Z.Qian S.Wong D.Marculescu R.Marculescu P.Bogdan Y.F.Teh X.S.Hu Y.Xue F.Ye K.Chan Q.Wu C.Ding D.Juan I.Pyo C.Su I.Huang K.Pan Y.Koh H.Chen G.Cheng S.Liu S.Wu
Talks about:
chip (6) network (5) power (5) design (3) low (3) schedul (2) perform (2) analysi (2) vector (2) scheme (2)

Person: Chi-Ying Tsui

DBLP DBLP: Tsui:Chi=Ying

Contributed to:

DAC 20142014
DATE 20132013
DATE 20122012
DAC 20072007
DAC 20062006
DATE 20052005
DATE v1 20042004
DAC 19971997
DAC 19961996
DAC 19941994
DAC 19931993
DAC 19921992

Wrote 12 papers:

DAC-2014-XueQBYT #analysis #framework #manycore #platform #scalability
Disease Diagnosis-on-a-Chip: Large Scale Networks-on-Chip based Multicore Platform for Protein Folding Analysis (YX, ZQ, PB, FY, CYT), p. 6.
DATE-2013-QianJBTMM #analysis #named #performance #using
SVR-NoC: a performance analysis tool for network-on-chips using learning-based support vector regression model (ZQ, DCJ, PB, CYT, DM, RM), pp. 354–357.
DATE-2012-QianTT #configuration management #self #using
A flit-level speedup scheme for network-on-chips using self-reconfigurable bi-directional channels (ZQ, YFT, CYT), pp. 1295–1300.
DAC-2007-LeungT #energy #synthesis
Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands (LFL, CYT), pp. 128–131.
DAC-2006-LeungT #performance #scheduling
Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems (LFL, CYT), pp. 833–838.
DATE-2005-LeungTH #energy #scheduling
Exploiting Dynamic Workload Variation in Low Energy Preemptive Task Scheduling (LFL, CYT, XSH), pp. 634–639.
DATE-v1-2004-WongT #configuration management #encoding #power management
Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus (SKW, CYT), pp. 130–135.
DAC-1997-TsuiCWDP #design #estimation #framework #power management #video
A Power Estimation Framework for Designing Low Power Portable Video Applications (CYT, KKC, QW, CSD, MP), pp. 421–424.
DAC-1996-TsuiMMP #performance
Improving the Efficiency of Power Simulators by Input Vector Compaction (CYT, RM, DM, MP), pp. 165–168.
DAC-1994-TsuiPD #approximate
Exact and Approximate Methods for Calculating Signal and Transition Probabilities in FSMs (CYT, MP, AMD), pp. 18–23.
DAC-1993-TsuiPD #composition #power management
Technology Decomposition and Mapping Targeting Low Power Dissipation (CYT, MP, AMD), pp. 68–73.
DAC-1992-PyoSHPKTCCLWD #automation #design
Application-Driven Design Automation for Microprocessor Design (IP, CLS, IJH, KRP, YSK, CYT, HTC, GC, SL, SW, AMD), pp. 512–517.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.