Travelled to:2 × Germany
2 × USA
5 × France
Collaborated with:L.Torres P.Benoit R.Elbaz P.Guillemin M.Bardouillet E.Carara G.M.Almeida F.G.Moraes B.Godard J.M.Daga D.Puschini F.Clermidy S.Senni R.M.Brum A.Gamatié B.Mussard C.Jalier D.Lattard A.A.Jerraya S.Z.Ahmed J.Eydoux L.Rouge J.Cuelle A.Martinez R.Garibotti L.Ost R.Busseuil M.kourouma C.Adeniyi-Jones M.Robert T.Gil C.Diou G.Cambon J.Galy C.Anguille C.Buatois J.Rigaud
Talks about:processor (4) memori (3) distribut (2) techniqu (2) encrypt (2) applic (2) embed (2) dynam (2) base (2) bus (2)
Person: Gilles Sassatelli
DBLP: Sassatelli:Gilles
Contributed to:
2015
20132011201020092007200620052002Wrote 10 papers:
- DATE-2015-SenniBTSGM
- Potential applications based on NVM emerging technologies (SS, RMB, LT, GS, AG, BM), pp. 1012–1017.
- DAC-2013-GaribottiOBkASR #distributed #embedded #memory management #multi #thread
- Simultaneous multithreading support in embedded distributed memory MPSoCs (RG, LO, RB, Mk, CAJ, GS, MR), p. 7.
- DATE-2011-CararaASM
- Achieving composability in NoC-based MPSoCs through QoS management at software level (EC, GMA, GS, FGM), pp. 407–412.
- DATE-2010-JalierLJSBT #mobile
- Heterogeneous vs homogeneous MPSoC approaches for a Mobile LTE modem (CJ, DL, AAJ, GS, PB, LT), pp. 184–189.
- DATE-2009-AhmedERCST #performance #pipes and filters #programmable #reduction
- Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor (SZA, JE, LR, JBC, GS, LT), pp. 184–189.
- DATE-2009-PuschiniCBST #distributed #energy #latency
- Dynamic and distributed frequency assignment for energy and latency constrained MP-SoC (DP, FC, PB, GS, LT), pp. 1564–1567.
- DATE-2007-GodardDTS #design #embedded #evaluation #reliability
- Evaluation of design for reliability techniques in embedded flash memories (BG, JMD, LT, GS), pp. 1593–1598.
- DAC-2006-ElbazTSGBM #encryption
- A parallelized way to provide data encryption and integrity checking on a processor-memory bus (RE, LT, GS, PG, MB, AM), pp. 506–509.
- DATE-2005-ElbazTSGABBR #bibliography #encryption #hardware
- Hardware Engines for Bus Encryption: A Survey of Existing Techniques (RE, LT, GS, PG, CA, MB, CB, JBR), pp. 40–45.
- DATE-2002-SassatelliTBGDCG #architecture #configuration management #scalability
- Highly Scalable Dynamically Reconfigurable Systolic Ring-Architecture for DSP Applications (GS, LT, PB, TG, CD, GC, JG), pp. 553–558.