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Travelled to:
2 × USA
3 × Germany
5 × France
Collaborated with:
P.Ienne M.Vuletic P.Bonzini P.Biswas G.Ansaloni P.G.Paulin K.Atasu N.D.Dutt N.Dutt K.Tanimura L.Righetti C.Alippi W.Fornaciari M.Sami J.Großschädl S.Tillich A.K.Verma S.Banerjee V.Choudhary
Talks about:
instruct (6) set (6) extens (5) reconfigur (4) processor (3) automat (3) specif (3) applic (3) coprocessor (2) architectur (2)

Person: Laura Pozzi

DBLP DBLP: Pozzi:Laura

Contributed to:

DATE 20112011
DATE 20092009
DATE 20072007
DATE 20062006
DATE 20052005
DAC 20042004
DATE v1 20042004
DAC 20032003
DATE 20022002
DATE 19991999

Wrote 13 papers:

DATE-2011-AnsaloniPTD #array #configuration management #scheduling
Slack-aware scheduling on Coarse Grained Reconfigurable Arrays (GA, LP, KT, ND), pp. 1513–1516.
DATE-2009-AnsaloniBP #architecture #embedded
Heterogeneous coarse-grained processing elements: A template architecture for embedded processing acceleration (GA, PB, LP), pp. 542–547.
DATE-2007-BonziniP #automation #polynomial #set
Polynomial-time subgraph enumeration for automated instruction set extension (PB, LP), pp. 1331–1336.
DATE-2007-PozziP #future of #question
A future of customizable processors: are we there yet? (LP, PGP), pp. 1224–1225.
DATE-2006-BiswasDIP #architecture #automation #functional #identification
Automatic identification of application-specific functional units with architecturally visible storage (PB, NDD, PI, LP), pp. 212–217.
DATE-2006-GrossschadlIPTV #algorithm #case study #design #encryption #set
Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography (JG, PI, LP, ST, AKV), pp. 218–223.
DATE-2005-BiswasBDPI #generative #named #set
ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement (PB, SB, NDD, LP, PI), pp. 1246–1251.
DAC-2004-BiswasCAPID #memory management #set
Introduction of local memory elements in instruction set extensions (PB, VC, KA, LP, PI, ND), pp. 729–734.
DAC-2004-VuleticPI #configuration management #memory management
Virtual memory window for application-specific reconfigurable coprocessors (MV, LP, PI), pp. 948–953.
DATE-v1-2004-VuleticRPI #configuration management #interface #operating system
Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors (MV, LR, LP, PI), p. 748.
DAC-2003-AtasuPI #architecture #automation #constraints
Automatic application-specific instruction-set extensions under microarchitectural constraints (KA, LP, PI), pp. 256–261.
DATE-2002-PozziVI #automation #embedded #identification
Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors (LP, MV, PI), p. 1138.
DATE-1999-AlippiFPS #approach #configuration management #design
A DAG-Based Design Approach for Reconfigurable VLIW Processors (CA, WF, LP, MS), pp. 778–779.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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