Travelled to:2 × France
2 × Germany
Collaborated with:M.Nicolaidis ∅ V.Pasca C.Rusu R.Locatelli M.Coppola N.Zergainoh Y.Zorian T.Karnik K.A.Bowman J.Tschanz S.Lu C.Tokunaga A.Raychowdhury M.M.Khellah J.Kulkarni V.De D.Avresky
Talks about:end (2) die (2) temporari (1) spidergon (1) techniqu (1) communic (1) reliabl (1) develop (1) concurr (1) resili (1)
Person: Lorena Anghel
DBLP: Anghel:Lorena
Contributed to:
2012201020092000Wrote 4 papers:
- DATE-2012-NicolaidisAZZKBTLTRKKDA #design #reliability
- Design for test and reliability in ultimate CMOS (MN, LA, NEZ, YZ, TK, KAB, JT, SLL, CT, AR, MMK, JK, VD, DA), pp. 677–682.
- DATE-2010-PascaARLC #3d #communication #fault
- Error resilience of intra-die and inter-die communication with 3D spidergon STNoC (VP, LA, CR, RL, MC), pp. 275–278.
- DATE-2009-Anghel #concurrent #development #topic
- HOT TOPIC — Concurrent SoC development and end-to-end planning (LA), p. 430.
- DATE-2000-AnghelN #detection #evaluation #fault #reduction
- Cost Reduction and Evaluation of a Temporary Faults Detecting Technique (LA, MN), pp. 591–598.