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Travelled to:
1 × France
4 × Germany
4 × USA
Collaborated with:
K.Roy S.Bhunia S.Gangopadhyay S.B.Nasir S.Mukhopadhyay Y.Lee M.M.Budnik A.Bansal B.C.Paul H.Mahmoodi-Meimand S.Datta N.Shukla M.Cotter A.Parihar M.Nicolaidis L.Anghel N.Zergainoh Y.Zorian T.Karnik K.A.Bowman J.Tschanz S.Lu C.Tokunaga M.M.Khellah J.Kulkarni V.De D.Avresky
Talks about:
current (3) test (3) analysi (2) leakag (2) comput (2) applic (2) under (2) power (2) model (2) dynam (2)

Person: Arijit Raychowdhury

DBLP DBLP: Raychowdhury:Arijit

Contributed to:

DAC 20152015
DAC 20142014
DATE 20142014
DATE 20122012
DAC 20062006
DATE 20062006
DATE 20052005
DATE v1 20042004
DAC 20032003

Wrote 9 papers:

DAC-2015-GangopadhyayNR #power management
Integrated power management in IoT devices under wide dynamic ranges of operation (SG, SBN, AR), p. 6.
Neuro Inspired Computing with Coupled Relaxation Oscillators (SD, NS, MC, AP, AR), p. 6.
DATE-2014-GangopadhyayLNR #adaptation #analysis #linear #modelling #performance
Modeling and analysis of digital linear dropout regulators with adaptive control for high efficiency under wide dynamic range digital loads (SG, YL, SBN, AR), pp. 1–6.
DATE-2012-NicolaidisAZZKBTLTRKKDA #design #reliability
Design for test and reliability in ultimate CMOS (MN, LA, NEZ, YZ, TK, KAB, JT, SLL, CT, AR, MMK, JK, VD, DA), pp. 677–682.
A high density, carbon nanotube capacitor for decoupling applications (MMB, AR, AB, KR), pp. 935–938.
DATE-2006-RaychowdhuryPBR #case study #comparative #power management
Ultralow power computing with sub-threshold leakage: a comparative study of bulk and SOI technologies (AR, BCP, SB, KR), pp. 856–861.
DATE-2005-BhuniaMRR #novel #testing
A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application (SB, HMM, AR, KR), pp. 1136–1141.
DATE-v1-2004-BhuniaRR #analysis #using
Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis (SB, AR, KR), pp. 704–705.
DAC-2003-MukhopadhyayRR #estimation #logic #modelling
Accurate estimation of total leakage current in scaled CMOS logic circuits based on compact current modeling (SM, AR, KR), pp. 169–174.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.