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Travelled to:
2 × Germany
3 × France
7 × USA
Collaborated with:
M.Engels S.Donnay S.Vernalde P.Schaumont P.Wambacq L.Rijnders H.D.Man R.Cmar P.Dobrovolný S.Guccione D.Verkest M.Badaroglu M.v.Heijningen G.Vandersteen Y.Rolain B.Gupta W.D.Rammelaere L.J.M.Claesen W.Maly L.Deferm J.Borel H.J.M.Veendrick J.B.Lewis R.Lauwereins C.Wheddon Y.Tanurhan L.Nachtergaele B.Vanhoof M.Peón G.Lafruit J.Bormans H.Ziad A.E.Gamal A.Broom C.Hamlin P.Magarshack Z.Or-Bach L.T.Pileggi J.Schoukens V.Gravot G.G.E.Gielen E.Berrebi P.Kission S.D.Troch J.Herluison J.Fréhel A.A.Jerraya N.Deo B.Zahiri J.Cong P.Lopresti C.B.Reynolds C.Rowen R.Simar
Talks about:
high (6) level (5) circuit (4) transceiv (3) design (3) simul (3) rate (3) nois (3) asic (3) reconfigur (2)

Person: Ivo Bolsens

DBLP DBLP: Bolsens:Ivo

Contributed to:

DAC 20042004
DAC 20032003
DATE 20022002
DATE 20012001
DAC 20002000
DATE 20002000
DAC 19991999
DATE 19991999
DAC 19981998
ED&TC 19971997
DAC 19961996
DAC 19891989

Wrote 18 papers:

DAC-2004-DeoZBCGLRRS #question #what
What happened to ASIC?: Go (recon)figure? (ND, BZ, IB, JC, BG, PL, CBR, CR, RS), p. 185.
DAC-2003-El-GamalBBHMOP #implementation #performance
Fast, cheap and under control: the next implementation fabric (AEG, IB, AB, CH, PM, ZOB, LTP), pp. 354–355.
DATE-2002-GuccioneVB #configuration management #design #platform
Design Technology for Networked Reconfigurable FPGA Platforms (SG, DV, IB), pp. 994–997.
DATE-2002-LewisBLWGT #configuration management #question #what
Reconfigurable SoC — What Will it Look Like? (JBL, IB, RL, CW, BG, YT), pp. 660–662.
DATE-2001-BadarogluHGDMGEB #generative #multi #scalability #simulation
High-level simulation of substrate noise generation from large digital circuits with multiple supplies (MB, MvH, VG, SD, HDM, GGEG, ME, IB), pp. 326–330.
DATE-2001-VandersteenWRSDEB #estimation #multi #performance
Efficient bit-error-rate estimation of multicarrier transceivers (GV, PW, YR, JS, SD, ME, IB), pp. 164–168.
DAC-2000-HeijningenBDEB #generative #power management #simulation
High-level simulation of substrate noise generation including power supply noise coupling (MvH, MB, SD, ME, IB), pp. 446–451.
DAC-2000-VandersteenWRDDEB #data flow #performance #simulation
A methodology for efficient high-level dataflow simulation of mixed-signal front-ends of digital telecom transceivers (GV, PW, YR, PD, SD, ME, IB), pp. 440–445.
DATE-2000-WambacqDDEB #communication #modelling
Compact Modeling of Nonlinear Distortion in Analog Communication Circuits (PW, PD, SD, ME, IB), pp. 350–354.
DAC-1999-NachtergaeleVPLBB #implementation #scalability #visual notation
Implementation of a Scalable MPEG-4 Wavelet-Based Visual Texture Compression System (LN, BV, MP, GL, JB, IB), pp. 333–336.
DAC-1999-SchaumontCVEB #behaviour #hardware #reuse
Hardware Reuse at the Behavioral Level (PS, RC, SV, ME, IB), pp. 784–789.
DATE-1999-BolsensMDBV #hybrid #integration
Single Chip or Hybrid System Integration (IB, WM, LD, JB, HJMV), p. 616–?.
DATE-1999-CmarRSVB #design #fixpoint #refinement
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement (RC, LR, PS, SV, IB), p. 271–?.
A Single-Package Solution for Wireless Transceivers (PW, SD, HZ, ME, HDM, IB), p. 425–?.
DAC-1998-SchaumontVREB #design #programming
A Programming Environment for the Design of Complex High Speed ASICs (PS, SV, LR, ME, IB), pp. 315–320.
EDTC-1997-SchaumontVREB #multi #synthesis
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications (PS, SV, LR, ME, IB), pp. 542–546.
DAC-1996-BerrebiKVTHFJB #control flow #data flow #synthesis
Combined Control Flow Dominated and Data Flow Dominated High-Level Synthesis (EB, PK, SV, SDT, JCH, JF, AAJ, IB), pp. 573–578.
DAC-1989-BolsensRCM #analysis #behaviour #debugging #logic
Electrical Debugging of Synchronous MOS VLSI Circuits Exploiting Analysis of the Intended Logic Behaviour (IB, WDR, LJMC, HDM), pp. 513–518.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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