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Travelled to:
3 × USA
4 × France
5 × Germany
Collaborated with:
C.Silvano G.Palermo R.Zafalon G.Mariani M.Sami D.Sciuto A.Bona E.Paone S.Xydis F.Robino I.Sander V.M.Sima K.Bertels A.Brankovic J.Jovic A.Gellert A.Florea L.N.Vintan L.Salvemini N.Vahabi D.Melpignano G.Haugou T.Lepley P.Avasare G.Vanmeerbeeck C.Ykman-Couvreur
Talks about:
explor (7) embed (6) architectur (5) system (5) design (5) space (5) power (4) methodolog (3) processor (3) energi (3)

Person: Vittorio Zaccaria

DBLP DBLP: Zaccaria:Vittorio

Contributed to:

DATE 20152015
DATE 20142014
DATE 20132013
DATE 20122012
DAC 20102010
DATE 20102010
DATE DF 20042004
DATE 20032003
SAC 20032003
DAC 20022002
DATE 20022002
DATE 20012001

Wrote 14 papers:

DATE-2015-PaoneRPZSS #constraints #framework #performance #platform
Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints (EP, FR, GP, VZ, IS, CS), pp. 736–741.
DATE-2014-MarianiPZS #design #named #predict #scheduling #simulation #using
DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling (GM, GP, VZ, CS), pp. 1–4.
DATE-2013-PaoneVZSMHL #embedded #manycore #modelling #platform #simulation
Improving simulation speed and accuracy for many-core embedded platforms with ensemble models (EP, NV, VZ, CS, DM, GH, TL), pp. 671–676.
DATE-2013-XydisPZS #architecture #compilation #framework #metamodelling #parametricity #synthesis
A meta-model assisted coprocessor synthesis framework for compiler/architecture parameters customization (SX, GP, VZ, CS), pp. 659–664.
DATE-2012-MarianiSPZSB #architecture #configuration management #design #multi #resource management #runtime #using
Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures (GM, VMS, GP, VZ, CS, KB), pp. 1379–1384.
DAC-2010-MarianiBPJZS #design #multi
A correlation-based design space exploration methodology for multi-processor systems-on-chip (GM, AB, GP, JJ, VZ, CS), pp. 120–125.
DATE-2010-GellertPZFVS #architecture #design #energy #predict #smt
Energy-performance design space exploration in SMT architectures exploiting selective load value predictions (AG, GP, VZ, AF, LNV, CS), pp. 271–274.
DATE-2010-MarianiAVYPSZ #design #framework #industrial #manycore #resource management #runtime
An industrial design space exploration framework for supporting run-time resource management on multi-core systems (GM, PA, GV, CYC, GP, CS, VZ), pp. 196–201.
DATE-DF-2004-BonaZZ #industrial #modelling #simulation
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip (AB, VZ, RZ), pp. 318–323.
DATE-2003-PalermoSZ #architecture #embedded
Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture (GP, CS, VZ), pp. 20182–20187.
SAC-2003-SalveminiSSSZZ #architecture #embedded #energy #performance #trade-off
A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems (LS, MS, DS, CS, VZ, RZ), pp. 672–678.
DAC-2002-BonaSSZSZ #clustering #embedded #energy #estimation #optimisation
Energy estimation and optimization of embedded VLIW processors based on instruction clustering (AB, MS, DS, VZ, CS, RZ), pp. 886–891.
DATE-2002-BonaSSZSZ #embedded #estimation #optimisation
An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores (AB, MS, DS, VZ, CS, RZ), p. 1128.
DATE-2001-SamiSSZZ #embedded
Exploiting data forwarding to reduce the power budget of VLIW embedded processors (MS, DS, CS, VZ, RZ), pp. 252–257.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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