BibSLEIGH — Gianluca

Travelled to:

1 × Cyprus
1 × USA
3 × France
7 × Germany

Collaborated with:

C.Silvano V.Zaccaria S.Xydis G.Mariani M.Monchiero O.Villa L.Fiorin G.Agosta A.Tumeo F.Ferrandi D.Sciuto I.S.Stamelakos F.Regazzoni P.Schaumont I.Verbauwhede E.Paone F.Robino I.Sander V.M.Sima K.Bertels A.Brankovic J.Jovic A.Gellert A.Florea L.N.Vintan P.Avasare G.Vanmeerbeeck C.Ykman-Couvreur M.Branca L.Camerini M.Ceriani

Talks about:

architectur (7) explor (7) system (6) design (6) space (6) multi (4) time (4) multiprocessor (3) reconfigur (3) framework (3)

Person: Gianluca Palermo

DBLP: Palermo:Gianluca

Contributed to:

2015

2014

2013

2012

2010

2009

2008

2006

2005

2004

2003

Wrote 16 papers:

DATE-2015-PaoneRPZSS #constraints #framework #performance #platform: Customization of OpenCL applications for efficient task mapping under heterogeneous platform constraints (EP, FR, GP, VZ, IS, CS), pp. 736–741.
DATE-2014-MarianiPZS #design #named #predict #scheduling #simulation #using: DeSpErate: Speeding-up design space exploration by using predictive simulation scheduling (GM, GP, VZ, CS), pp. 1–4.
DATE-2014-SilvanoPXS #architecture #manycore: Voltage island management in near threshold manycore architectures to mitigate dark silicon (CS, GP, SX, ISS), pp. 1–6.
DATE-2013-XydisPS #configuration management: Thermal-aware datapath merging for coarse-grained reconfigurable processors (SX, GP, CS), pp. 1649–1654.
DATE-2013-XydisPZS #architecture #compilation #framework #metamodelling #parametricity #synthesis: A meta-model assisted coprocessor synthesis framework for compiler/architecture parameters customization (SX, GP, VZ, CS), pp. 659–664.
DATE-2012-MarianiSPZSB #architecture #configuration management #design #multi #resource management #runtime #using: Using multi-objective design space exploration to enable run-time resource management for reconfigurable architectures (GM, VMS, GP, VZ, CS, KB), pp. 1379–1384.
DAC-2010-MarianiBPJZS #design #multi: A correlation-based design space exploration methodology for multi-processor systems-on-chip (GM, AB, GP, JJ, VZ, CS), pp. 120–125.
DATE-2010-GellertPZFVS #architecture #design #energy #predict #smt: Energy-performance design space exploration in SMT architectures exploiting selective load value predictions (AG, GP, VZ, AF, LNV, CS), pp. 271–274.
DATE-2010-MarianiAVYPSZ #design #framework #industrial #manycore #resource management #runtime: An industrial design space exploration framework for supporting run-time resource management on multi-core systems (GM, PA, GV, CYC, GP, CS, VZ), pp. 196–201.
DATE-2010-TumeoRPFS #architecture #configuration management #implementation #multi #recognition #reliability: A reconfigurable multiprocessor architecture for a reliable face recognition implementation (AT, FR, GP, FF, DS), pp. 319–322.
DATE-2009-FiorinPS #monitoring #runtime: MPSoCs run-time monitoring through Networks-on-Chip (LF, GP, CS), pp. 558–561.
DATE-2008-TumeoBCCMPFS #multi #realtime: A Dual-Priority Real-Time Multiprocessor System on FPGA for Automotive Applications (AT, MB, LC, MC, MM, GP, FF, DS), pp. 1039–1044.
DATE-2006-MonchieroPSV #hardware #optimisation #performance: Power/performance hardware optimization for synchronization intensive applications in MPSoCs (MM, GP, CS, OV), pp. 606–611.
DATE-2005-VillaSVMP #framework #integration #memory management #multi #performance: Fast Dynamic Memory Integration in Co-Simulation Frameworks for Multiprocessor System on-Chip (OV, PS, IV, MM, GP), pp. 804–805.
SAC-2004-AgostaPS #architecture #design #embedded #multi #power management #program transformation #source code: Multi-objective co-exploration of source code transformations and design space architectures for low-power embedded systems (GA, GP, CS), pp. 891–896.
DATE-2003-PalermoSZ #architecture #embedded: Power-Performance System-Level Exploration of a MicroSPARC2-Based Embedded Architecture (GP, CS, VZ), pp. 20182–20187.