Travelled to:1 × France
1 × Germany
5 × USA
Collaborated with:∅ H.T.Heineken P.K.Nag J.Khare Y.Lin M.Marek-Sadowska C.H.Ouyang A.H.El-Maleh T.E.Marchok J.Rajski P.Simon W.A.Pleskacz J.E.Nelson T.Zanon R.Desineni J.G.Brown N.Patil R.D.(.Blanton
Talks about:design (7) manufactur (4) test (4) interfac (3) vlsi (3) part (2) cost (2) technolog (1) irregular (1) distribut (1)
Person: Wojciech Maly
DBLP: Maly:Wojciech
Contributed to:
2007
20062001199819971995199419871986Wrote 11 papers:
- DAC-2007-MalyLM #design
- OPC-Free and Minimally Irregular IC Design Style (WM, YWL, MMS), pp. 954–957.
- DATE-2006-NelsonZDBPMB #fault
- Extraction of defect density and size distributions from wafer sort test results (JEN, TZ, RD, JGB, NP, WM, RD(B), pp. 913–918.
- DAC-2001-Maly #design
- IC Design in High-Cost Nanometer-Technologies Era (WM), pp. 9–14.
- DATE-1998-HeinekenM #design #named #performance #trade-off
- Performance — Manufacturability Tradeoffs in IC Design (HTH, WM), pp. 563–567.
- DATE-1998-MalyNHK #interface
- Design-Manufacturing Interface: Part I — Vision (WM, PKN, HTH, JK), pp. 550–556.
- DATE-1998-MalyNOHKS #interface
- Design-Manufacturing Interface: Part II — Applications (WM, PKN, CHO, HTH, JK, PS), pp. 557–562.
- DAC-1997-HeinekenKMNOP #interface
- CAD at the Design-Manufacturing Interface (HTH, JK, WM, PKN, CHO, WAP), pp. 321–326.
- DAC-1995-El-MalehMRM #on the #testing
- On Test Set Preservation of Retimed Circuits (AHEM, TEM, JR, WM), pp. 176–182.
- DAC-1994-Maly #design #perspective
- Cost of Silicon Viewed from VLSI Design Perspective (WM), pp. 135–142.
- DAC-1987-Maly #fault #modelling #testing
- Realistic Fault Modeling for VLSI Testing (WM), pp. 173–180.
- DAC-1986-Maly #order #sequence #testing
- Optimal order of the VLSI IC testing sequence (WM), pp. 560–566.