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Travelled to:
3 × France
4 × Germany
4 × USA
Collaborated with:
X.Li L.Zhang G.Yan H.Li Y.Wang J.Gao B.Fu J.Dong X.He X.Li Q.Xu C.Wang H.Lu J.Wang Y.Li M.Guo X.Liang Y.Yu S.Ren
Talks about:
processor (4) scheme (3) memori (3) power (3) chip (3) base (3) no (3) multicor (2) topolog (2) exploit (2)

Person: Yinhe Han

DBLP DBLP: Han:Yinhe

Contributed to:

DAC 20152015
DATE 20142014
DAC 20132013
DATE 20132013
DATE 20122012
HPCA 20122012
DAC 20112011
DATE 20112011
DATE 20102010
DATE 20092009
DATE 20082008

Wrote 14 papers:

DAC-2015-WangH0LL #logic #memory management #named
ProPRAM: exploiting the transparent logic resources in non-volatile memory for near data computing (YW, YH, LZ, HL, XL), p. 6.
DAC-2015-WangHWLL #assembly #memory management #named
RADAR: a case for retention-aware DRAM assembly and repair in future FGR DRAM memory (YW, YH, CW, HL, XL), p. 6.
DATE-2014-HeYH0 #design #named #power management
SuperRange: Wide operational range power delivery design for both STV and NTV computing (XH, GY, YH, XL), pp. 1–6.
DAC-2013-LuYHF0 #named
RISO: relaxed network-on-chip isolation for cloud processors (HL, GY, YH, BF, XL), p. 6.
DATE-2013-LiYHL #adaptation #named #smarttech #user interface
SmartCap: user experience-oriented power adaptation for smartphone’s application processor (XL, GY, YH, XL), pp. 57–60.
DATE-2012-GaoWHZL #clustering #concurrent #debugging #manycore
A clustering-based scheme for concurrent trace in debugging NoC-based multicore systems (JG, JW, YH, LZ, XL), pp. 27–32.
HPCA-2012-YanLHLGL #architecture #hybrid #manycore #named #performance
AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture (GY, YL, YH, XL, MG, XL), pp. 287–298.
Wear rate leveling: lifetime enhancement of PRAM with endurance variation (JD, LZ, YH, YW, XL), pp. 972–977.
DATE-2011-GaoHL #debugging #multi
Eliminating data invalidation in debugging multiple-clock chips (JG, YH, XL), pp. 691–696.
DATE-2011-WangZHLL #memory management
Flex memory: Exploiting and managing abundant off-chip optical bandwidth (YW, LZ, YH, HL, XL), pp. 968–973.
Accelerating Lightpath setup via broadcasting in binary-tree waveguide in Optical NoCs (BF, YH, HL, XL), pp. 933–936.
DATE-2010-ZhangYDHRL #manycore #symmetry
Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors (LZ, YY, JD, YH, SR, XL), pp. 1566–1571.
DATE-2009-YanHL #detection #fault #online
A unified online Fault Detection scheme via checking of Stability Violation (GY, YH, XL), pp. 496–501.
DATE-2008-ZhangHXL #fault #manycore #using
Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology (LZ, YH, QX, XL), pp. 891–896.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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