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Travelled to:
3 × France
3 × Germany
3 × USA
Collaborated with:
G.Deconinck V.D.Florio D.Verkest S.Vernalde J.A.Peperstraete F.Catthoor B.Mei M.Truyens W.Rosseel M.Adé H.D.Man T.V.Achteren S.Graeber P.Wauters M.Engels J.Mignolet V.Nollet P.Coene J.B.Lewis I.Bolsens C.Wheddon B.Gupta Y.Tanurhan R.Belmans F.Bacchini J.M.Rabaey A.Cox F.Lane U.Ramacher D.Witt A.Cuomo G.Martin P.Groeneveld K.Maex P.v.d.Steeg R.Wilson C.Wong P.Marchal P.Yang A.S.Prayati N.Cossement O.Botti F.Cassinari S.Donatelli A.Bobbio A.Klein H.Kufner E.M.Thurner E.Verhulst
Talks about:
fault (5) reconfigur (4) softwar (4) design (4) toler (4) data (4) implement (3) parallel (3) applic (3) architectur (2)

Person: Rudy Lauwereins

DBLP DBLP: Lauwereins:Rudy

Facilitated 1 volumes:

DATE 2007Ed

Contributed to:

DATE 20142014
DAC 20122012
DAC 20052005
DATE v1 20042004
DATE v2 20042004
DATE 20032003
DATE 20022002
DATE 20012001
PDP 20012001
PDP 20002000
PDP 19991999
PDP 19981998
DAC 19971997
PDP 19961996

Wrote 17 papers:

Interfacing to living cells (RL), pp. 1–3.
DAC-2012-Lauwereins #physics
Biomedical electronics serving as physical environmental and emotional watchdogs (RL), pp. 1–5.
DAC-2005-BacchiniRCLLRW #platform
Wireless platforms: GOPS for cents and MilliWatts (FB, JMR, AC, FL, RL, UR, DW), pp. 351–352.
DATE-v1-2004-CatthoorCMGLMSW #design #how #problem #question #scalability
How Can System-Level Design Solve the Interconnect Technology Scaling Problem? (FC, AC, GM, PG, RL, KM, PvdS, RW), pp. 332–339.
DATE-v2-2004-MeiVVL #architecture #case study #configuration management #design #matrix
Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study (BM, SV, DV, RL), pp. 1224–1229.
DATE-2003-MeiVVML #architecture #configuration management #parallel #scheduling #using
Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling (BM, SV, DV, HDM, RL), pp. 10296–10301.
DATE-2003-MignoletNCVVL #configuration management #design #framework
Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip (JYM, VN, PC, DV, SV, RL), pp. 10986–10993.
DATE-2002-AchterenDCL #reuse
Data Reuse Exploration Techniques for Loop-Dominated Application (TVA, GD, FC, RL), pp. 428–435.
DATE-2002-LewisBLWGT #configuration management #question #what
Reconfigurable SoC — What Will it Look Like? (JBL, IB, RL, CW, BG, YT), pp. 660–662.
DATE-2001-WongMYCMPCLV #concurrent #summary
Task concurrency management methodology summary (CW, PM, PY, FC, HDM, ASP, NC, RL, DV), p. 813.
PDP-2001-FlorioDL #approach #fault tolerance
The Recovery Language Approach for Software-Implemented Fault Tolerance (VDF, GD, RL), p. 418–?.
PDP-2001-FlorioDLG #design #implementation
Design and Implementation of a Data Stabilizing Software Tool (VDF, GD, RL, SG), pp. 50–56.
PDP-2000-BottiFDLCDBKKTV #approach #fault tolerance #reuse
The TIRAN approach to reusing software implemented fault tolerance (OB, VDF, GD, RL, FC, SD, AB, AK, HK, EMT, EV), pp. 325–332.
PDP-1999-DeconinckTFRLB #embedded #fault tolerance #framework #parallel
A framework backbone for software fault tolerance in embedded parallel applications (GD, MT, VDF, WR, RL, RB), pp. 189–195.
PDP-1998-FlorioDTRL #distributed #embedded #fault tolerance #hypermedia #injection #monitoring #parallel #source code
A hypermedia distributed application for monitoring and fault-injection in embedded fault-tolerant parallel programs (VDF, GD, MT, WR, RL), pp. 349–355.
DAC-1997-AdeLP #data flow #graph #memory management
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets (MA, RL, JAP), pp. 64–69.
PDP-1996-WautersELP #data flow
Cyclo-Dynamic Dataflow (PW, ME, RL, JAP), pp. 319–326.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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