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Travelled to:
3 × Germany
6 × France
6 × USA
Collaborated with:
S.Pravossoudovitch A.Virazel L.Dilillo C.Landrault M.Bastian A.Bosio A.Ney V.Gouin N.Badereddine S.Caffiau L.Guittet D.L.Scapin P.M.Rosinger B.M.Al-Hashimi D.Dumas D.Gizopoulos K.Roy N.Nicolici X.Wen Y.A.Ameur F.Besnard G.Pierra J.Potier C.Kolski P.Forbrig B.David C.D.Tran H.Ezzedine Y.Bonhomme L.Guiller A.Touati P.Bernardi M.S.Reorda L.B.Zordan A.Todri R.A.Fonseca J.Azevedo A.Todri-Sanial G.Prenat J.Alvarez-Herault K.Mackay
Talks about:
test (8) sram (7) power (6) design (5) fault (5) diagnosi (3) analysi (3) core (3) cell (3) low (3)

Person: Patrick Girard

DBLP DBLP: Girard:Patrick

Contributed to:

DATE 20152015
DATE 20132013
DATE 20122012
DAC 20102010
DATE 20092009
HCI p2 20092009
HCI p1 20092009
DATE 20082008
DATE 20072007
DATE 20062006
DAC 20052005
DATE v1 20042004
SEKE 19951995
DAC 19921992

Wrote 16 papers:

DATE-2015-TouatiBDGVBR #functional #power management #source code #testing
Exploring the impact of functional test programs re-used for power-aware testing (AT, AB, LD, PG, AV, PB, MSR), pp. 1277–1280.
DATE-2013-ZordanBDGTVB #fault #power management
Test solution for data retention faults in low-power SRAMs (LBZ, AB, LD, PG, AT, AV, NB), pp. 442–447.
DATE-2012-AzevedoVBDGTPAM #architecture #fault
Impact of resistive-open defects on the heat current of TAS-MRAM architectures (JA, AV, AB, LD, PG, ATS, GP, JAH, KM), pp. 532–537.
DAC-2010-FonsecaDBGPVB #analysis #reliability #simulation #statistics
A statistical simulation method for reliability analysis of SRAM core-cells (RAF, LD, AB, PG, SP, AV, NB), pp. 853–856.
DATE-2009-NeyDGPVBG #fault
A new design-for-test technique for SRAM core-cell stability faults (AN, LD, PG, SP, AV, MB, VG), pp. 1344–1348.
HCI-NIMT-2009-CaffiauGGS #design #interactive
Hierarchical Structure: A Step for Jointly Designing Interactive Software Dialog and Task Model (SC, PG, LG, DLS), pp. 664–673.
HCI-NT-2009-KolskiFDGTE #architecture #design #evaluation #interactive
Agent-Based Architecture for Interactive System Design: Current Approaches, Perspectives and Evaluation (CK, PF, BD, PG, CDT, HE), pp. 624–633.
DATE-2008-GizopoulosRGNW #power management #testing
Power-Aware Testing and Test Strategies for Low Power Devices (DG, KR, PG, NN, XW).
A Design-for-Diagnosis Technique for SRAM Write Drivers (AN, PG, SP, AV, MB, VG), pp. 1480–1485.
DATE-2007-NeyGLPVB #analysis #fault
Slow write driver faults in 65nm SRAM technology: analysis and March test solution (AN, PG, CL, SP, AV, MB), pp. 528–533.
DATE-2006-DililloRAG #process #reduction
Minimizing test power in SRAM through reduction of pre-charge activity (LD, PMR, BMAH, PG), pp. 1159–1164.
DAC-2005-DililloGPVB #analysis #comparison #fault #injection
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies (LD, PG, SP, AV, MB), pp. 857–862.
DATE-v1-2004-BonhommeGGLPV #design #power management
Design of Routing-Constrained Low Power Scan Chains (YB, PG, LG, CL, SP, AV), pp. 62–67.
SEKE-1995-Ait-AmeurBGPP #metaprogramming #specification
Formal Specification and Metaprogramming in the EXPRESS Language (YAA, FB, PG, GP, JCP), pp. 181–188.
EDAC-1994-DumasGLP #effectiveness #fault
Effectiveness of a Variable Sampling Time Strategy for Delay Fault Diagnosis (DD, PG, CL, SP), pp. 518–523.
DAC-1992-GirardLP #approach #novel
A Novel Approach to Delay-Fault Diagnosis (PG, CL, SP), pp. 357–360.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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