BibSLEIGH corpus
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Open Knowledge
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Travelled to:
1 × China
1 × France
3 × Germany
6 × USA
Collaborated with:
M.J.Schulte D.J.Palframan M.H.Lipasti A.A.Sinkar J.Lee S.Z.Gilani J.H.Ahn U.R.Karpuzcu H.R.Ghasemi H.Wang A.F.Farahani K.Morrow I.Akturk S.C.Draper J.Torrellas J.Adriaens K.Compton C.Park G.Byun R.Bai T.Kgil D.Sylvester T.N.Mudge Y.H.Son S.Lee O.Seongil S.Kwon P.Aguilera Ahmed H. M. O. Abulila Vikram Sharma Mailthody Zaid Qureshi Jian Huang 0006 J.Xiong Wen-Mei W. Hwu
Talks about:
power (7) processor (5) architectur (4) voltag (4) memori (4) effici (4) comput (4) energi (3) optim (3) near (3)

Person: Nam Sung Kim

DBLP DBLP: Kim:Nam_Sung

Contributed to:

HPCA 20152015
DATE 20142014
HPCA 20142014
HPCA 20132013
DAC 20122012
DATE 20122012
HPCA 20122012
DATE 20112011
HPCA 20112011
DAC 20092009
DATE 20052005
ASPLOS 20192019

Wrote 18 papers:

HPCA-2015-FarahaniAMK #architecture #memory management #named #standard
NDA: Near-DRAM acceleration architecture leveraging commodity DRAM devices and standard memory modules (AFF, JHA, KM, NSK), pp. 283–295.
HPCA-2015-PalframanKL #energy #fault #named #performance
iPatch: Intelligent fault patching to improve energy efficiency (DJP, NSK, MHL), pp. 428–438.
HPCA-2015-SonLSKKA #architecture #named
CiDRA: A cache-inspired DRAM resilience architecture (YHS, SL, OS, SK, NSK, JHA), pp. 502–513.
HPCA-2015-WangPBAK #alloy #architecture #memory management #named
Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems (HW, CJP, GB, JHA, NSK), pp. 296–308.
DATE-2014-AguileraLFMSK #algorithm #clustering #multi #process
Process variation-aware workload partitioning algorithms for GPUs supporting spatial-multitasking (PA, JL, AFF, KM, MJS, NSK), pp. 1–6.
HPCA-2014-KarpuzcuAK #named #towards
Accordion: Toward soft Near-Threshold Voltage Computing (URK, IA, NSK), pp. 72–83.
HPCA-2014-PalframanKL #fault
Precision-aware soft error protection for GPUs (DJP, NSK, MHL), pp. 49–59.
HPCA-2013-GilaniKS #power management
Power-efficient computing for compute-intensive GPGPU applications (SZG, NSK, MJS), pp. 330–341.
HPCA-2013-KarpuzcuSKT #energy #named #towards
EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing (URK, AAS, NSK, JT), pp. 542–553.
DAC-2012-GhasemiSSK #effectiveness #power management
Cost-effective power delivery to support per-core voltage domains for power-constrained processors (HRG, AAS, MJS, NSK), pp. 56–61.
DATE-2012-SinkarWK #manycore #optimisation #performance
Workload-aware voltage regulator optimization for power efficient multi-core processors (AAS, HW, NSK), pp. 1134–1137.
HPCA-2012-AdriaensCKS #multi
The case for GPGPU spatial multitasking (JA, KC, NSK, MJS), pp. 79–90.
DATE-2011-GilaniKS #memory management #optimisation
Scratchpad memory optimizations for digital signal processing applications (SZG, NSK, MJS), pp. 974–979.
DATE-2011-PalframanKL #detection #fault #low cost
Time redundant parity for low-cost transient error detection (DJP, NSK, MHL), pp. 52–57.
HPCA-2011-GhasemiDK #architecture #using
Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors (HRG, SCD, NSK), pp. 38–49.
DAC-2009-LeeK #manycore #optimisation #throughput #using
Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating (JL, NSK), pp. 47–50.
DATE-2005-BaiKKSM #multi #trade-off
Power-Performance Trade-Offs in Nanometer-Scale Multi-Level Caches Considering Total Leakage (RB, NSK, TK, DS, TNM), pp. 650–651.
ASPLOS-2019-AbulilaMQHKXH #named
FlatFlash: Exploiting the Byte-Accessibility of SSDs within a Unified Memory-Storage Hierarchy (AHMOA, VSM, ZQ, JH0, NSK, JX, WMWH), pp. 971–985.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.