BibSLEIGH corpus
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Open Knowledge
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Travelled to:
1 × China
1 × Sweden
1 × Taiwan
2 × Germany
3 × France
6 × USA
Collaborated with:
M.Zhao M.Li Q.Li E.H.Sha J.Hu Y.He Y.Zhao T.Liu Y.Chen Y.Liu C.Fu A.Orailoglu W.Tseng Q.Zhuge X.Chen L.Shi L.Jiang Y.Zhang M.Qiu K.Wu M.Xie K.Qiu Y.Huang W.Tian E.Chen Z.Shao D.Goswami A.Masrur R.Schneider S.Chakraborty J.Zheng C.Pan Y.Chen N.Jiang C.Xu J.Li Y.Xu Y.He D.Zhang X.Sheng J.Li T.Wu H.Yang Q.Li C.Gao
Talks about:
memori (12) volatil (8) system (7) awar (7) regist (6) energi (6) power (6) embed (5) pcm (5) non (5)

Person: Chun Jason Xue

DBLP DBLP: Xue:Chun_Jason

Contributed to:

DAC 20152015
DATE 20152015
DAC 20142014
DATE 20142014
DATE 20132013
LCTES 20132013
DAC 20122012
LCTES 20122012
DAC 20112011
DATE 20112011
SAC 20112011
DAC 20102010
LCTES 20102010
DATE 20082008

Wrote 27 papers:

DAC-2015-ChenCX #classification #named #power management #video
DaTuM: dynamic tone mapping technique for OLED display power saving based on video classification (XC, YC, CJX), p. 6.
DAC-2015-LiZHLHX #automation #compilation #performance #stack
Compiler directed automatic stack trimming for efficient non-volatile processors (QL, MZ, JH, YL, YH, CJX), p. 6.
DAC-2015-XieZPHLX #energy
Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor (MX, MZ, CP, JH, YL, CJX), p. 6.
DAC-2015-ZhangLSLWXY #energy #migration #scheduling
Deadline-aware task scheduling for solar-powered nonvolatile sensor nodes with global energy migration (DZ, YL, XS, JL, TW, CJX, HY), p. 6.
DATE-2015-FuLX #energy #memory management
Race to idle or not: balancing the memory sleep time with DVS for energy minimization (CF, ML, CJX), pp. 13–18.
DATE-2015-FuZLX #manycore #memory management
Maximizing common idle time on multi-core processors with shared memory (CF, YZ, ML, CJX), pp. 900–903.
DATE-2015-LiSGWXZS #memory management #performance #reduction
Maximizing IO performance via conflict reduction for flash memory storage systems (QL, LS, CG, KW, CJX, QZ, EHMS), pp. 904–907.
DATE-2015-ZhaoLXLHX #cyber-physical #energy #reduction
Software assisted non-volatile register reduction for energy harvesting based cyber-physical system (MZ, QL, MX, YL, JH, CJX), pp. 567–572.
DAC-2014-QiuLX #performance #power management
Write Mode Aware Loop Tiling for High Performance Low Power Volatile PCM (KQ, QL, CJX), p. 6.
DAC-2014-ShiWZXS #memory management #reduction
Retention Trimming for Wear Reduction of Flash Memory Storage Systems (LS, KW, MZ, CJX, EHMS), p. 6.
DAC-2014-ZhaoJZX #process
SLC-enabled Wear Leveling for MLC PCM Considering Process Variation (MZ, LJ, YZ, CJX), p. 6.
DATE-2014-LiHCXJX #embedded #memory management #stack
A wear-leveling-aware dynamic stack for PCM memory in embedded systems (QL, YH, YC, CJX, NJ, CX), pp. 1–4.
DATE-2013-GoswamiMSXC #design #multi
Multirate controller design for resource- and schedule-constrained automotive ECUs (DG, AM, RS, CJX, SC), pp. 1123–1126.
DATE-2013-HuZXTS #embedded #hybrid #in memory #memory management
Software enabled wear-leveling for hybrid PCM main memory on embedded systems (JH, QZ, CJX, WCT, EHMS), pp. 599–602.
DATE-2013-LiSLXCX #adaptation
Cache coherence enabled adaptive refresh for volatile STT-RAM (JL, LS, QL, CJX, YC, YX), pp. 1247–1250.
DATE-2013-ZhaoOX #process #synthesis
Profit maximization through process variation aware high level synthesis with speed binning (MZ, AO, CJX), pp. 176–181.
LCTES-2013-LiJZHX #compilation #performance #power management
Compiler directed write-mode selection for high performance low power volatile PCM (QL, LJ, YZ, YH, CJX), pp. 101–110.
DAC-2012-ChenZCZX #mobile #scalability #streaming #video
Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices (XC, JZ, YC, MZ, CJX), pp. 1000–1005.
LCTES-2012-HuangZX #architecture #clustering #embedded #realtime
WCET-aware re-scheduling register allocation for real-time embedded systems with clustered VLIW architecture (YH, MZ, CJX), pp. 31–40.
LCTES-2012-LiZXH #embedded #hybrid
Compiler-assisted preferred caching for embedded systems with STT-RAM based hybrid cache (QL, MZ, CJX, YH), pp. 109–118.
DAC-2011-LiuZXL #clustering #hybrid #in memory #memory management #power management
Power-aware variable partitioning for DSPs with hybrid PRAM and DRAM main memory (TL, YZ, CJX, ML), pp. 405–410.
DATE-2011-HuXZTS #energy #hybrid #memory management #performance #towards
Towards energy efficient hybrid on-chip Scratch Pad Memory with non-volatile memory (JH, CJX, QZ, WCT, EHMS), pp. 746–751.
DATE-2011-LiuOXL #energy #reduction
Register allocation for simultaneous reduction of energy and peak temperature on registers (TL, AO, CJX, ML), pp. 20–25.
SAC-2011-TianXLC #optimisation #order
Loop fusion and reordering for register file optimization on stream processors (WT, CJX, ML, EC), pp. 560–565.
DAC-2010-HuXTHQS #embedded #migration #process
Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation (JH, CJX, WCT, YH, MQ, EHMS), pp. 350–355.
LCTES-2010-LiXLZ #analysis #approximate #architecture #memory management
Analysis and approximation for bank selection instruction minimization on partitioned memory architecture (ML, CJX, TL, YZ), pp. 1–8.
DATE-2008-XueSSQ #clustering #constraints #effectiveness #memory management #scheduling
Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints (CJX, EHMS, ZS, MQ), pp. 1202–1207.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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