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Travelled to:
2 × Germany
2 × USA
3 × France
Collaborated with:
P.Girard A.Virazel A.Bosio S.Pravossoudovitch M.Bastian N.Badereddine P.M.Rosinger B.M.Al-Hashimi A.Touati P.Bernardi M.S.Reorda L.B.Zordan A.Todri R.A.Fonseca A.Ney V.Gouin J.Azevedo A.Todri-Sanial G.Prenat J.Alvarez-Herault K.Mackay
Talks about:
test (5) sram (5) power (3) core (3) cell (3) analysi (2) resist (2) impact (2) defect (2) fault (2)

Person: Luigi Dilillo

DBLP DBLP: Dilillo:Luigi

Contributed to:

DATE 20152015
DATE 20132013
DATE 20122012
DAC 20102010
DATE 20092009
DATE 20062006
DAC 20052005

Wrote 7 papers:

DATE-2015-TouatiBDGVBR #functional #power management #source code #testing
Exploring the impact of functional test programs re-used for power-aware testing (AT, AB, LD, PG, AV, PB, MSR), pp. 1277–1280.
DATE-2013-ZordanBDGTVB #fault #power management
Test solution for data retention faults in low-power SRAMs (LBZ, AB, LD, PG, AT, AV, NB), pp. 442–447.
DATE-2012-AzevedoVBDGTPAM #architecture #fault
Impact of resistive-open defects on the heat current of TAS-MRAM architectures (JA, AV, AB, LD, PG, ATS, GP, JAH, KM), pp. 532–537.
DAC-2010-FonsecaDBGPVB #analysis #reliability #simulation #statistics
A statistical simulation method for reliability analysis of SRAM core-cells (RAF, LD, AB, PG, SP, AV, NB), pp. 853–856.
DATE-2009-NeyDGPVBG #fault
A new design-for-test technique for SRAM core-cell stability faults (AN, LD, PG, SP, AV, MB, VG), pp. 1344–1348.
DATE-2006-DililloRAG #process #reduction
Minimizing test power in SRAM through reduction of pre-charge activity (LD, PMR, BMAH, PG), pp. 1159–1164.
DAC-2005-DililloGPVB #analysis #comparison #fault #injection
Resistive-open defect injection in SRAM core-cell: analysis and comparison between 0.13 µm and 90 nm technologies (LD, PG, SP, AV, MB), pp. 857–862.

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