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Travelled to:
1 × Italy
2 × USA
4 × France
4 × Germany
Collaborated with:
F.Fummi G.Pravadelli S.Vinco V.Guarnieri N.Deganello R.Filippozzi F.Stefanni H.Liu L.P.Carloni M.Hampton F.Letombe V.Bertacco D.Chatterjee A.M.Kaushik H.D.Patel M.Petricca A.Sassone E.Macii M.Poncino
Talks about:
rtl (8) verif (6) tlm (5) base (4) function (3) abstract (3) design (3) transactor (2) testbench (2) generat (2)

Person: Nicola Bombieri

DBLP DBLP: Bombieri:Nicola

Contributed to:

DATE 20152015
DATE 20142014
DAC 20132013
DATE 20132013
DATE 20122012
DAC 20102010
DATE 20092009
DATE 20082008
DATE 20072007
DATE 20062006
SFM 20062006

Wrote 13 papers:

DATE-2015-BombieriFPS #abstraction #verification
RTL property abstraction for TLM assertion-based verification (NB, RF, GP, FS), pp. 85–90.
DATE-2014-GuarnieriPSVBFMP #embedded #monitoring #verification
A cross-level verification methodology for digital IPs augmented with embedded timing monitors (VG, MP, AS, SV, NB, FF, EM, MP), pp. 1–6.
DAC-2013-BombieriLFC #c++ #synthesis
A method to abstract RTL IP blocks into C++ code and enable high-level synthesis (NB, HYL, FF, LPC), p. 9.
DATE-2013-BertaccoCBFVKP #on the #using
On the use of GP-GPUs for accelerating compute-intensive EDA applications (VB, DC, NB, FF, SV, AMK, HDP), pp. 1357–1366.
DATE-2012-BombieriFG #fault #framework #functional #named #simulation #verification
FAST-GP: An RTL functional verification framework based on fault simulation on GP-GPUs (NB, FF, VG), pp. 562–565.
DAC-2010-BombieriFP #abstraction #embedded
Abstraction of RTL IPs into embedded software (NB, FF, GP), pp. 24–29.
DATE-2009-BombieriFPHL #functional #verification
Functional qualification of TLM verification (NB, FF, GP, MH, FL), pp. 190–195.
DATE-2009-BombieriFPV #generative
Correct-by-construction generation of device drivers based on RTL testbenches (NB, FF, GP, SV), pp. 1500–1505.
DATE-2008-BombieriDF #automation #design #generative
Integrating RTL IPs into TLM Designs Through Automatic Transactor Generation (NB, ND, FF), pp. 15–20.
DATE-2008-BombieriFP #communication #interface
A Mutation Model for the SystemC TLM 2.0 Communication Interfaces (NB, FF, GP), pp. 396–401.
DATE-2007-BombieriFP #design #functional #incremental #refinement #validation
Incremental ABV for functional validation of TL-to-RTL design refinement (NB, FF, GP), pp. 882–887.
DATE-2006-BombieriFP #evaluation #on the #reuse #verification
On the evaluation of transactor-based verification for reusing TLM assertions and testbenches at RTL (NB, FF, GP), pp. 1007–1012.
SFM-2006-BombieriFP #design #hardware #simulation #verification
Hardware Design and Simulation for Verification (NB, FF, GP), pp. 1–29.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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