BibSLEIGH — Kartik

Travelled to:

4 × France
5 × Germany
6 × USA

Collaborated with:

M.R.Choudhury Q.Zhou X.Yang A.Zukoski M.H.B.Jamaa G.D.Micheli J.Li V.Chandra R.C.Aitken J.Guo M.Wartell S.Iyer K.Du P.J.Varman A.C.Antoulas Y.Yoon K.Ringgenberg S.Rixner K.Sun D.C.Sorensen J.Rakshit R.Wan K.T.Lam

Talks about:

logic (10) circuit (5) time (5) memori (4) error (4) transistor (3) reliabl (3) power (3) interconnect (2) technolog (2)

Person: Kartik Mohanram

DBLP: Mohanram:Kartik

Contributed to:

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

Wrote 20 papers:

DAC-2015-RakshitWLGM #design #power management #robust: Monolayer transition metal dichalcogenide and black phosphorus transistors for low power robust SRAM design (JR, RW, KTL, JG, KM), p. 6.
DATE-2014-LiM #memory management: Write-once-memory-code phase change memory (JL, KM), pp. 1–6.
DATE-2013-MohanramWI #certification #compilation #memory management #named #order #reduction: Mempack: an order of magnitude reduction in the cost, risk, and time for memory compiler certification (KM, MW, SI), pp. 1490–1493.
DATE-2012-DuVM #latency #performance #reliability: High performance reliable variable latency carry select addition (KD, PJV, KM), pp. 1257–1262.
DAC-2011-ZukoskiYM #logic: Universal logic modules based on double-gate carbon nanotube transistors (AZ, XY, KM), pp. 884–889.
DATE-2011-YangM #design #robust: Robust 6T Si tunneling transistor SRAM design (XY, KM), pp. 740–745.
DATE-2011-ZukoskiCM #logic #synthesis: Reliability-driven don’t care assignment for logic synthesis (AZ, MRC, KM), pp. 1560–1565.
DATE-2010-ChoudhuryCMA #logic #performance: Analytical model for TDDB-based performance degradation in combinational logic (MRC, VC, KM, RCA), pp. 423–428.
DATE-2010-ChoudhuryCMA10a #fault #named #online: TIMBER: Time borrowing and error relaying for online timing error resilience (MRC, VC, KM, RCA), pp. 1554–1559.
DATE-2010-JamaaMM #logic #power management: Power consumption of logic circuits in ambipolar carbon nanotube technology (MHBJ, KM, GDM), pp. 303–306.
DAC-2009-ChoudhuryM #logic #lookahead #optimisation #using: Timing-driven optimization using lookahead logic circuits (MRC, KM), pp. 390–395.
DATE-2009-ChoudhuryM #fault #logic: Masking timing errors on speed-paths in logic circuits (MRC, KM), pp. 87–92.
DATE-2009-JamaaMM #library #logic #multi #novel #synthesis: Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis (MHBJ, KM, GDM), pp. 622–627.
DAC-2008-ChoudhuryYGM: Technology exploration for graphene nanoribbon FETs (MRC, YY, JG, KM), pp. 272–277.
DATE-2008-ChoudhuryM #approximate #concurrent #detection #fault #logic: Approximate logic circuits for low overhead, non-intrusive concurrent error detection (MRC, KM), pp. 903–908.
DATE-2007-ChoudhuryM #analysis #logic #reliability #scalability: Accurate and scalable reliability analysis of logic circuits (MRC, KM), pp. 1454–1459.
DATE-2007-ChoudhuryRRM #interactive #memory management: Interactive presentation: Single-ended coding techniques for off-chip interconnects to commodity memory (MRC, KR, SR, KM), pp. 1072–1077.
DAC-2006-ZhouM #energy #estimation: Elmore model for energy estimation in RC trees (QZ, KM), pp. 965–970.
DATE-2006-ZhouSMS #analysis #composition #grid #power management #scalability #using: Large power grid analysis using domain decomposition (QZ, KS, KM, DCS), pp. 27–32.
DAC-2005-ZhouMA #reduction: Structure preserving reduction of frequency-dependent interconnect (QZ, KM, ACA), pp. 939–942.