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Travelled to:
4 × France
5 × Germany
5 × USA
Collaborated with:
S.Cherubal G.Srinivasan S.Sen H.W.Choi A.V.Gomes R.K.Roy R.I.Hartley A.Goyal M.Swaminathan F.Taenzler Y.S.Dhillon A.U.Diril R.Voorakaranam P.Pant V.De N.Nagi J.A.Abraham D.Banerjee S.K.Devarakond N.Tzou D.Bhatta S.Hsiao V.Natarajan R.Senguttuvan S.Bhattacharya
Talks about:
circuit (8) test (8) use (7) system (4) jitter (4) analog (4) power (3) optim (3) base (3) decomposit (2)

Person: Abhijit Chatterjee

DBLP DBLP: Chatterjee:Abhijit

Contributed to:

DAC 20132013
DATE 20132013
DATE 20092009
DAC 20082008
DATE 20082008
DATE 20062006
DATE 20052005
DATE v1 20042004
DATE 20022002
DATE 20012001
DATE 19991999
DAC 19971997
DAC 19931993
DAC 19901990

Wrote 16 papers:

DAC-2013-BanerjeeDSC #adaptation #constraints #energy #performance #realtime
Real-time use-aware adaptive MIMO RF receiver systems for energy efficiency under BER constraints (DB, SKD, SS, AC), p. 7.
DATE-2013-TzouBHC #bound #composition #using
Periodic jitter and bounded uncorrelated jitter decomposition using incoherent undersampling (NT, DB, SWH, AC), pp. 1667–1672.
DATE-2009-GoyalSC #novel #self
A novel self-healing methodology for RF Amplifier circuits based on oscillation principles (AG, MS, AC), pp. 1656–1661.
DAC-2008-SenNSC #adaptation #named #power management #process
Pro-VIZOR: process tunable virtually zero margin low power adaptive RF for wireless systems (SS, VN, RS, AC), pp. 492–497.
DATE-2008-ChoiC #testing #using
Digital bit stream jitter testing using jitter expansion (HWC, AC), pp. 1468–1473.
DATE-2006-SrinivasanTC #automation #low cost #multi #online #platform
Online RF checkers for diagnosing multi-gigahertz automatic test boards on low cost ATE platforms (GS, FT, AC), pp. 658–663.
DATE-2005-DhillonDC #analysis #optimisation
Soft-Error Tolerance Analysis and Optimization of Nanometer Circuits (YSD, AUD, AC), pp. 288–293.
DATE-v1-2004-SrinivasanBCC #metric #performance #using
Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements: Uses and Benefit (GS, SB, SC, AC), pp. 280–285.
DATE-2002-VoorakaranamCC #agile #framework #testing
A Signature Test Framework for Rapid Production Testing of RF Circuits (RV, SC, AC), pp. 186–191.
DATE-2001-CherubalC #generative #parametricity #testing
Test generation based diagnosis of device parameters for analog circuits (SC, AC), pp. 596–602.
DATE-1999-CherubalC #fault #functional #parametricity #using
Parametric Fault Diagnosis for Analog Systems Using Functional Mapping (SC, AC), p. 195–?.
DATE-1999-GomesC #testing #using
Minimal Length Diagnostic Tests for Analog Circuits using Test History (AVG, AC), pp. 189–194.
DAC-1997-PantDC #energy #logic #network #optimisation #power management #random
Device-Circuit Optimization for Minimal Energy and Power Consumption in CMOS Random Logic Networks (PP, VD, AC), pp. 403–408.
DAC-1993-ChatterjeeR #architecture #composition #multi #optimisation
An Architectural Transformation Program for Optimization of Digital Systems by Multi-Level Decomposition (AC, RKR), pp. 343–348.
DAC-1993-NagiCA #fault #named
DRAFTS: Discretized Analog Circuit Fault Simulator (NN, AC, JAA), pp. 509–514.
DAC-1990-ChatterjeeH #approach #clustering
A New Simultaneous Circuit Partitioning and Chip Placement Approach Based on Simulated Annealing (AC, RIH), pp. 36–39.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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