BibSLEIGH — Michael_S

Travelled to:

4 × USA
7 × Germany
9 × France

Collaborated with:

S.Sheng L.Fang W.Wu ∅ K.Chandrasekar M.Li M.Elbayoumi M.Y.ElNainay D.Bakshi N.He X.Cheng V.C.Vimjam M.Syal K.Gulrajani S.T.Chakradhar M.Banga N.P.Rahagude B.Li K.Takayama E.M.Rudnick J.H.Patel S.K.Misra S.Sengupta Y.Zheng C.Huang L.Zhang M.R.Prasad T.Sidle S.M.Yardi T.L.Martin D.S.Ha A.Giani V.D.Agrawal M.Choudhury V.N.Kravets A.Sullivan S.H.Park J.Leidig L.T.Li E.A.Fox N.J.Short K.E.Hoyle A.L.Abbott

Talks about:

effici (7) sequenti (6) base (6) use (6) algorithm (5) comput (5) sat (5) identif (4) circuit (4) novel (4)

Person: Michael S. Hsiao

DBLP: Hsiao:Michael_S=

Contributed to:

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

2001

2000

1999

1998

1997

Wrote 28 papers:

DAC-2014-ElbayoumiCKSHE #algorithm #named #parallel #synthesis: TACUE: A Timing-Aware Cuts Enumeration Algorithm for Parallel Synthesis (ME, MC, VNK, AS, MSH, MYE), p. 6.
DATE-2013-BakshiH #reduction #smt #using: LFSR seed computation and reduction using SMT-based fault-chaining (DB, MSH), pp. 1071–1076.
DATE-2013-ElbayoumiHE #concurrent #diagrams #manycore #novel #platform: A novel concurrent cache-friendly binary decision diagram construction for multi-core platforms (ME, MSH, MYE), pp. 1427–1430.
DATE-2012-ChandrasekarMSH #debugging #design #industrial: A scan pattern debugger for partial scan industrial designs (KC, SKM, SS, MSH), pp. 558–561.
DATE-2012-LiH #analysis #logic #named #performance #reliability: RAG: An efficient reliability analysis of logic circuits on graphics processing units (ML, MSH), pp. 316–319.
DATE-2011-BangaRH #testing: Design-for-test methodology for non-scan at-speed testing (MB, NPR, MSH), pp. 191–196.
TPDL-2011-ParkLLFSHAH #analysis #collaboration #empirical #library #research: Experiment and Analysis Services in a Fingerprint Digital Library for Collaborative Research (SHP, JL, LTL, EAF, NJS, KEH, ALA, MSH), pp. 179–191.
DATE-2010-LiZHH #logic #optimisation #synthesis: Reversible logic synthesis through ant colony optimization (ML, YZ, MSH, CH), pp. 307–310.
DATE-2009-HeH #algorithm #encoding #performance #verification: An efficient path-oriented bitvector encoding width computation algorithm for bit-precise verification (NH, MSH), pp. 1602–1607.
DATE-2008-ChengH #invariant #mining #verification: Simulation-Directed Invariant Mining for Software Verification (XC, MSH), pp. 682–687.
DATE-2008-FangH #algorithm #approximate #performance #satisfiability: A Fast Approximation Algorithm for MIN-ONE SAT (LF, MSH), pp. 1087–1090.
DATE-2008-WuH #algorithm #design #performance #validation: Efficient Design Validation Based on Cultural Algorithms (WW, MSH), pp. 402–407.
DATE-2007-FangH #hybrid #performance #satisfiability: A new hybrid solution to boost SAT solver performance (LF, MSH), pp. 1307–1313.
DAC-2006-VimjamH #identification #induction #performance #satisfiability: Fast illegal state identification for improving SAT-based induction (VCV, MSH), pp. 241–246.
DAC-2006-WuH #bound #constraints #equivalence #mining: Mining global constraints for improving bounded sequential equivalence checking (WW, MSH), pp. 743–748.
DAC-2005-ZhangPHS #abstraction #satisfiability #using: Dynamic abstraction using SAT-based BMC (LZ, MRP, MSH, TS), pp. 754–757.
DATE-2005-ChandrasekarH #fault #generative #incremental #integration #learning #performance #satisfiability #testing: Integration of Learning Techniques into Incremental Satisfiability for Efficient Path-Delay Fault Test Generation (KC, MSH), pp. 1002–1007.
DATE-2005-YardiHMH #multi #power management #quality: Quality-Driven Proactive Computation Elimination for Power-Aware Multimedia Processing (SMY, MSH, TLM, DSH), pp. 340–345.
DATE-v1-2004-LiHS #novel #performance #satisfiability: A Novel SAT All-Solutions Solver for Efficient Preimage Computation (BL, MSH, SS), pp. 272–279.
DATE-2003-ShengH #novel #performance #using: Efficient Preimage Computation Using A Novel Success-Driven ATPG (SS, MSH), pp. 10822–10827.
DATE-2003-SyalH #algorithm #fault #identification #low cost #novel: A Novel, Low-Cost Algorithm for Sequentially Untestable Fault Identification (MS, MSH), pp. 10316–10321.
DAC-2002-ShengTH #effectiveness #safety #using: Effective safety property checking using simulation-based sequential ATPG (SS, KT, MSH), pp. 813–818.
DATE-2002-Hsiao #fault #identification: Maximizing Impossibilities for Untestable Fault Identification (MSH), pp. 949–953.
DATE-2001-GianiSHA #performance: Efficient spectral techniques for sequential ATPG (AG, SS, MSH, VDA), pp. 204–208.
DATE-2000-GulrajaniH #identification #logic #multi: Multi-Node Static Logic Implications for Redundancy Identification (KG, MSH), pp. 729–733.
DATE-1999-Hsiao #estimation #optimisation #scalability #search-based #using: Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits (MSH), p. 175–?.
DATE-1998-HsiaoC #performance #sequence: State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits (MSH, STC), pp. 577–582.
EDTC-1997-HsiaoRP #generative #testing #traversal #using: Sequential circuit test generation using dynamic state traversal (MSH, EMR, JHP), pp. 22–28.